1. Field
One embodiment of the invention relates to a pipeline high-level synthesis system and a pipeline high-level synthesis method which receives a high-level description as an input to thereby generate a pipelined circuit.
2. Description of the Related Art
As is known, in the case of a current high-level synthesis tool, when two or more accesses are generated for the same array in a loop, it becomes basically impossible to realize pipeline synthesis. In this case, satisfactory performance cannot be obtained, resulting in abandonment of a high-level design, or involving high-cost update of the high-level description to be input to the high-level synthesis system. In particular, such a problem is prominent in video image processing.
Jpn. Pat. Appln. Publication No. 2003-30261 discloses a technique that prevents an access conflict between threads when a plurality of threads operating in parallel concurrently access a shared memory. However, the above patent document does not refer to a technique in which a circuit is pipelined for a desired performance, that is, it does not disclose a technical concept purposed for the realization of a one-cycle pipeline at all.